Frontier AI Research · San Francisco
OpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI.
We are seeking a highly capable Implementation Engineer & Technologist to drive silicon construction and optimization for next-generation AI chips. This is a senior hands-on individual-contributor role for an engineer who combines strong technical breadth with the ability to go deep quickly, solve hard problems, and land results in collaboration with cross-functional teams.
You will operate across architecture, circuits, memory, RTL, physical implementation, and integration technologies to turn amb itious product goals into manufacturable silicon. This role is not limited to analysis or pathfinding—you will be expected to develop solutions, prototype ideas, drive execution, and close critical gaps.
The ideal candidate is a hands-on generalist with strong engineering judgment, deep circuit intuition, broad semiconductor knowledge, and a habit of using AI tools to move faster and make better decisions.
Partner with architecture and system teams to translate product goals into executable silicon construction strategies.
Drive hands-on optimization of power, performance, area, cost, and reliability across the silicon stack.
Develop and implement solutions spanning circuits, memory, RTL, physical design, and integration.
Use and build AI-driven tools, flows, and methodologies to accelerate silicon implementation.
Evaluate new technologies and convert them into reliable product constructions optimized for performance, performance/TCO, and performance/W.
BS with 12+ years, MS with 10+ years, or PhD with 6+ years of relevant industry experience in chip design or implementation.
Strong hands-on expertise in circuits and implementation-driven PPA optimization.
Deep knowledge of semiconductor technologies including memory, advanced nodes, packaging, and 3D integration.
Hands-on experience with RTL design and physical implementation through tapeout.
Proven ability to work across disciplines and solve complex technical problems end-to-end.
Strong use of AI tools for engineering productivity, analysis, coding, or design optimization.
Excellent technical communication and collaboration skills.
Strong first-principles understanding of AI chip architectures and training/inference workloads.
Experience improving silicon products through innovations in performance, power, cost, yield, or reliability.
Experience with HBM, SRAM, memory hierarchy design, or memory-centric optimization.
Experience building internal tools, models, or automation used by engineering teams.
Research lab experience and/or PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field.
To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations.
About OpenAI
OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity.
We are an equal opportunity employer, and we do not discriminate on the basis of race, religion, color, national origin, sex, sexual orientation, age, veteran status, disability, genetic information, or other applicable legally protected characteristic.
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Background checks for applicants will be administered in accordance with applicable law, and qualified applicants with arrest or conviction records will be considered for employment consistent with those laws, including the San Francisco Fair Chance Ordinance, the Los Angeles County Fair Chance Ordinance for Employers, and the California Fair Chance Act, for US-based candidates. For unincorporated Los Angeles County workers: we reasonably believe that criminal history may have a direct, adverse and negative relationship with the following job duties, potentially resulting in the withdrawal of a conditional offer of employment: protect computer hardware entrusted to you from theft, loss or damage; return all computer hardware in your possession (including the data contained therein) upon termination of employment or end of assignment; and maintain the confidentiality of proprietary, confidential, and non-public information. In addition, job duties require access to secure and protected information technology systems and related data security obligations.
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